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1/16 november 2002 m48z32v 3.3v, 256 kbit (32 kbit x 8) zeropower ? sram features summary integrated, ultra low power sram, and power-fail control circuit read cycle time equals write cycle time automatic power-fail chip deselect and write protection write protect voltages: (v pfd = power-fail deselect voltage) C m48z32v: 2.7v v pfd 3.0v ultra-low standby current figure 1. logic diagram figure 2. 44-pin, hatless soic package table 1. signal names ai04787 15 a0-a14 w dq0-dq7 v cc m48z32v g v ss 8 b + e a0-a14 address inputs dq0-dq7 data inputs / outputs e chip enable input g output enable input w write enable input v cc supply voltage v ss ground b + positive battery pin nc not connected 44 1 soh44 (mt)
m48z32v 2/16 table of contents description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 soic connections (figure 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 block diagram (figure 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 maximum rating. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 absolute maximum ratings (table 2.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 dc and ac parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 operating and ac measurement conditions (table 3.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ac measurement load circuit (figure 5.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 capacitance (table 4.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 dc characteristics (table 5.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 operating modes (table 6.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 read mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 read mode ac waveforms (figure 6.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 read mode ac characteristics (table 7.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 write enable controlled, write mode ac waveforms (figure 7.) . . . . . . . . . . . . . . . . . . . . . . . . 9 chip enable controlled, write mode ac waveforms (figure 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . 9 write mode ac characteristics (table 8.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 data retention mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 power down/up mode ac waveforms (figure 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 power down/up ac characteristics (table 9.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 power down/up trip points dc characteristics (table 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 v cc noise and negative going transients . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 supply voltage protection (figure 10.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 package mechanical information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3/16 m48z32v description the m48z32v zeropower ? ram is a 32 kbit x 8, non-volatile static ram that integrates power- fail deselect circuitry and battery control logic on a single die. the 44-pin, 330mil soic provides a battery pin for an external, user-supplied battery. this is all that is required to fully non-volatize the sram. figure 3. soic connections note: nf, pin 7 must be tied to v ss . ai04786 22 44 43 v ss 1 a2 nf nc nc a3 nc nc g ce nc nc w nc nc a10 v cc m48z32v 10 2 5 6 7 8 9 11 12 13 14 15 21 40 39 36 35 34 33 32 31 30 29 28 a4 a5 a9 a13 3 4 38 37 42 41 a1 a0 dq7 dq5 dq0 dq1 dq3 dq4 dq6 16 17 18 19 20 27 26 25 24 23 nc nc nc a12 a6 a7 b + nc nc nc a11 a14 dq2 a8
m48z32v 4/16 figure 4. block diagram maximum rating stressing the device above the rating listed in the absolute maximum ratings table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicat- ed in the operating sections of this specification is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect de- vice reliability. refer also to the stmicroelectronics sure program and other rel- evant quality documents. table 2. absolute maximum ratings note: 1. reflow at peak temperature of 215c to 225c for < 60 seconds (total thermal budget not to exceed 180c for between 90 a nd 120 seconds). caution: negative undershoots below C0.3v are not allowed on any pin while in the battery back-up mode. ai04788 lithium cell v pfd v cc v ss voltage sense and switching circuitry 32k x 8 sram array a0-a14 dq0-dq7 e w g power user supplied symbol parameter value unit t a ambient operating temperature grade 1 0 to 70 c grade 6 C40 to 85 c t stg storage temperature (v cc off, oscillator off) soic C55 to 125 c t sld (1) lead solder temperature for 10 seconds 260 c v io input or output voltages C0.3 to v cc + 0.3 v v cc supply voltage C0.3 to 4.6 v i o output current 20 ma p d power dissipation 1 w
5/16 m48z32v dc and ac parameters this section summarizes the operating and mea- surement conditions, as well as the dc and ac characteristics of the device. the parameters in the following dc and ac characteristic tables are derived from tests performed under the measure- ment conditions listed in the relevant tables. de- signers should check that the operating conditions in their projects match the measurement condi- tions when using the quoted parameters. table 3. operating and ac measurement conditions note: 1. output hi-z is defined as the point where data is no longer driven. figure 5. ac measurement load circuit table 4. capacitance note: 1. effective capacitance measured with power supply at 3.3v; sampled only, not 100% tested. 2. at 25c, f = 1mhz. 3. outputs deselected. parameter (1) m48z32v unit supply voltage (v cc ) 3.0 to 3.6 v ambient operating temperature (t a ) grade 1 0 to 70 c grade 6 C40 to 85 c load capacitance (c l ) 50 pf input rise and fall times 5ns input pulse voltages 0 to 3 v input and output timing ref. voltages 1.5 v ai04789 c l = 50pf or 5pf c l includes jig capacitance 645 device under test 1.75v symbol parameter (1,2) min max unit c in input capacitance 10 pf c io (3) input / output capacitance 10 pf
m48z32v 6/16 table 5. dc characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c or C40 to 85c; v cc = 3.0 to 3.6v (except where noted). 2. outputs deselected. 3. negative spikes of C1v allowed for up to 10ns once per cycle. operating modes the m48z32v also has its own power-fail detect circuit. the control circuitry constantly monitors the single power supply for an out of tolerance condition. when v cc is out of tolerance, the circuit write protects the sram, providing a high degree of data security in the midst of unpredictable sys- tem operation brought on by low v cc . as v cc falls below approximately v so , the control circuitry con- nects the battery which maintains data until valid power returns. table 6. operating modes note: x = v ih or v il ; v so = battery back-up switchover voltage. 1. see table 10, page 12 for details. sym parameter test condition (1) min typ max unit i li input leakage current 0v v in v cc 1 a i lo (2) output leakage current 0v v out v cc 1 a i bat battery current t a = 40c; v cc = 0v v bat = 3v 0.2 1.2 a i cc1 supply current i o = 0ma; cycle time = min e = 0.2v, other input = v cc C 2v or 0.2v 45 ma i cc2 supply current (ttl standby) e = v ih 800 a i cc3 supply current (cmos standby) e = v cc C 0.2v 500 a v il (3) input low voltage C0.3 0.8 v v ih input high voltage 2.2 v cc + 0.3 v v ol output low voltage i ol = 2.1ma 0.4 v v oh output high voltage i oh = C1ma 0.8v cc v mode v cc e g w dq0-dq7 power deselect 3.0 to 3.6v v ih x x high z standby write v il x v il d in active read v il v il v ih d out active read v il v ih v ih high z active deselect v so to v pfd (min) (1) x x x high z cmos standby deselect v so (1) x x x high z battery back-up mode
7/16 m48z32v read mode the m48z32v is in the read mode whenever w (write enable) is high, e (chip enable) is low. the device architecture allows ripple-through ac- cess of data from eight of 262,144 locations in the static storage array. thus, the unique address specified by the 15 address inputs defines which one of the 32,768 bytes of data is to be accessed. valid data will be available at the data i/o pins within address access time (t avqv ) after the last address input signal is stable, providing that the e and g access times are also satisfied. if the e and g access times are not met, valid data will be available after the latter of the chip enable access time (t elqv ) or output enable access time (t glqv ). the state of the eight three-state data i/o signals is controlled by e and g . if the outputs are activat- ed before t avqv , the data lines will be driven to an indeterminate state until t avqv . if the address in- puts are changed while e and g remain active, output data will remain valid for output data hold time (t axqx ) but will go indeterminate until the next address access. figure 6. read mode ac waveforms note: write enable (w ) = high. ai00925 tavav tavqv taxqx telqv telqx tehqz tglqv tglqx tghqz valid a0-a14 e g dq0-dq7 valid
m48z32v 8/16 table 7. read mode ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c or C40 to 85c; v cc = 3.0 to 3.6v (except where noted). 2. c l = 5pf (see figure 5, page 5). symbol parameter (1) m48z32v unit C35 min max t avav read cycle time 35 ns t avqv address valid to output valid 35 ns t elqv chip enable low to output valid 35 ns t glqv output enable low to output valid 15 ns t elqx (2) chip enable low to output transition 5 ns t glqx (2) output enable low to output transition 0 ns t ehqz (2) chip enable high to output hi-z 13 ns t ghqz (2) output enable high to output hi-z 13 ns t axqx address transition to output transition 5 0 ns
9/16 m48z32v write mode the m48z32v is in the write mode whenever w and e are low. the start of a write is referenced from the latter occurring falling edge of w or e . a write is terminated by the earlier rising edge of w or e . the addresses must be held valid through- out the cycle. e or w must return high for a mini- mum of t ehax from chip enable or t whax from write enable prior to the initiation of another read or write cycle. data-in must be valid t d- vwh prior to the end of write and remain valid for t whdx afterward. g should be kept high during write cycles to avoid bus contention; although, if the output bus has been activated by a low on e and g , a low on w will disable the outputs t wlqz after w falls. figure 7. write enable controlled, write mode ac waveforms figure 8. chip enable controlled, write mode ac waveforms ai05662 tavav twhax tdvwh data input a0-a14 e w dq0-dq7 valid tavwh twlwh tavwl twlqz twhdx twhqx ai00927 tavav tehax tdveh a0-a14 e w dq0-dq7 valid taveh tavel tavwl teleh tehdx data input
m48z32v 10/16 table 8. write mode ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c or C40 to 85c; v cc = 3.0 to 3.6v (except where noted). 2. c l = 5pf (see figure 5, page 5). 3. if e goes low simultaneously with w going low, the outputs remain in the high impedance state. symbol parameter (1) m48z32v unit C35 min max t avav write cycle time 35 ns t av wl address valid to write enable low 0 ns t av el address valid to chip enable low 0 ns t wlwh write enable pulse width 25 ns t eleh chip enable low to chip enable high 25 ns t whax write enable high to address transition 0 ns t ehax chip enable high to address transition 0 ns t dvwh input valid to write enable high 12 ns t dveh input valid to chip enable high 12 ns t whdx write enable high to input transition 0 ns t ehdx chip enable high to input transition 0 ns t wlqz (2,3) write enable low to output hi-z 13 ns t avwh address valid to write enable high 25 ns t ave h address valid to chip enable high 25 ns t whqx (2,3) write enable high to output transition 5 ns
11/16 m48z32v data retention mode with valid v cc applied, the m48z32v operates as a conventional bytewide? static ram. should the supply voltage decay, the ram will automati- cally power-fail deselect, write protecting itself when v cc falls within the v pfd (max), v pfd (min) window. all outputs become high impedance, and all inputs are treated as don't care. note: a power failure during a write cycle may corrupt data at the currently addressed location, but does not jeopardize the rest of the ram's con- tent. at voltages below v pfd (min), the user can be assured the memory will be in a write protected state, provided the v cc fall time is not less than t f . the m48z32v may respond to transient noise spikes on v cc that reach into the deselect window during the time the device is sampling v cc . there- fore, decoupling of the power supply lines is rec- ommended. when v cc drops below v so , the control circuit switches power to the external battery which pre- serves data. as system power returns and v cc rises above v so , the battery is disconnected, and the power supply is switched to external v cc . write protec- tion continues until v cc reaches v pfd (min) plus t rec (min). normal ram operation can resume t rec after v cc exceeds v pfd (max). for more information on battery storage life refer to the application note an1012. figure 9. power down/up mode ac waveforms table 9. power down/up ac characteristics note: 1. valid for ambient operating temperature: t a = 0 to 70c or C40 to 85c; v cc = 3.0 to 3.6v (except where noted). 2. v pfd (max) to v pfd (min) fall time of less than t f may result in deselection/write protection not occurring until 200s after v cc pass- es v pfd (min). 3. v pfd (min) to v ss fall time of less than t fb may cause corruption of ram data. 4. t rec (min) = 20ms for industrial temperature grade (6) device. symbol parameter (1) min max unit t pd e or w at v ih before power down 0s t f (2) v pfd (max) to v pfd (min) v cc fall time 300 s t fb (3) v pfd (min) to v ss v cc fall time 10 s t r v pfd (min) to v pfd (max) v cc rise time 10 s t rb v ss to v pfd (min) v cc rise time 1s t rec (4) v pfd (max) to inputs recognized 40 200 ms ai01168c v cc inputs (per control input) outputs don't care high-z tf tfb tr tpd trb tdr valid valid (per control input) recognized recognized v pfd (max) v pfd (min) v so trec
m48z32v 12/16 table 10. power down/up trip points dc characteristics note: 1. all voltages referenced to v ss . 2. valid for ambient operating temperature: t a = 0 to 70c or C40 to 85c; v cc = 3.0 to 3.6v (except where noted). v cc noise and negative going transients i cc transients, including those produced by output switching, can produce voltage fluctuations, re- sulting in spikes on the v cc bus. these transients can be reduced if capacitors are used to store en- ergy which stabilizes the v cc bus. the energy stored in the bypass capacitors will be released as low going spikes are generated or energy will be absorbed when overshoots occur. a ceramic by- pass capacitor value of 0.1f (see figure 10) is recommended in order to provide the needed fil- tering. in addition to transients that are caused by normal sram operation, power cycling can generate neg- ative voltage spikes on v cc that drive it to values below v ss by as much as one volt. these negative spikes can cause data corruption in the sram while in battery backup mode. to protect from these voltage spikes, st recommends connecting a schottky diode from v cc to v ss (cathode con- nected to v cc , anode to v ss ). (schottky diode 1n5817 is recommended for through hole and mbrs120t3 is recommended for surface mount). figure 10. supply voltage protection symbol parameter (1,2) min typ max unit v pfd power-fail deselect voltage 2.7 2.85 3.0 v v so battery back-up switchover voltage v pfd C 100mv v ai02169 v cc 0.1 f device v cc v ss
13/16 m48z32v part numbering table 11. ordering information scheme for a list of available options (e.g., speed, package) or for further information on any aspect of this device, please contact the st sales office nearest to you. example: m48z 32v C35 mt 1 tr device type m48z supply voltage and write protect voltage 32v = v cc = 3.0 to 3.6v; v pfd = 2.7 to 3.0v speed C35 = 35ns package mt = 44-lead, hatless soic temperature range 1 = 0 to 70c 6 = C40 to 85c shipping method for soic blank = tubes tr = tape & reel
m48z32v 14/16 package mechanical information figure 11. soh44 C 44-lead plastic, hatless, small package outline note: drawing is not to scale. table 12. soh44 C 44-lead plastic, hatless, small package mechanical data symbol mm inch typ min max typ min max a 3.05 0.120 a1 0.05 0.36 0.002 0.014 a2 2.34 2.69 0.092 0.106 b 0.36 0.46 0.014 0.018 c 0.15 0.32 0.006 0.012 d 17.71 18.49 0.697 0.728 e 8.23 8.89 0.324 0.350 e 0.81 C C 0.032 C C h 11.51 12.70 0.453 0.500 l 0.41 1.27 0.016 0.050 0 8 0 8 n44 44 cp 0.10 0.004 soh-c e n d c l a1 1 h a cp be a2
15/16 m48z32v revision history table 13. revision history date rev. # revision details october 2002 1.0 first issue 11/07/02 1.1 update absolute maximum ratings, dc characteristics (table 2, 5)
m48z32v 16/16 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the co nsequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specifications mentioned in this publicati on are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics prod ucts are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectro nics. the st logo is registered trademark of stmicroelectronics all other names are the property of their respective owners. ? 2002 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - israel - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. www.st.com

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